这是一个创建于 2405 天前的主题，其中的信息可能已经有所发展或是发生改变。
招聘信息:
地点上海北京，薪资 open，欢迎来撩~~
资深 /高级芯片验证工程师
提交简历
工作地点：北京、上海 工作经验：5 或 3 年 教育经历：硕士 工作性质：全职
职位描述
1.Develop test plans, tests and verification infrastructure for complex IP's/sub-system/SOC's
2.Create verification environment for both directed and random verification
3.Create reusable bus functional models, monitors, checkers and scoreboards
4.Drive functional coverage driven verification closure
5.Work with architects, designers and post-silicon teams
职位要求
1.MS with 5+ or 3+ years of experience in design verification
2.Experience with RISC CPU (RISCV/MIPS/ARM) related IPs verification are highly desirable
3.Experience with USB/MIPI_CSI/MIPI_DSI or other high speed interface IPs verification are highly desirable
4.Experience with Deep Learning Accelerator related IPs verification are highly desirable
5.Excellent knowledge of popular EDA simulation tools (VCS or equivalent simulation tools, debug tools like Debussy, Simvision)
6.Experience in System Verilog or similar HVL is highly desirable
7.C++ programming language experience desirable
8.Scripting knowledge (Perl/shell)
9.Excellent communication skills and ability to lead highly competent team.
资深 /高级芯片设计工程师
工作地点：北京、上海 工作经验：5 或 3 年 教育经历：硕士 工作性质：全职
职位描述
1.Participate in RISCV or Deep Learning Accelerator or other SOC IP design for all frontend phase
2.Specification define
3.RTL implementation
4.Analysis and optimization for performance
5.Analysis and optimization for power
6.Analysis and optimization for timing
7.Design flow: lint/synthesis/sta/formal check
8.Silicon debugging
职位要求
1.MS with 5+ or 3+ years of experience in ASIC design
2.Experience with RISC CPU (RISCV/MIPS/ARM) related IPs design are highly desirable
3.Experience with USB/MIPI_CSI/MIPI_DSI or other high speed interface IPs design are highly desirable
4.Experience with Deep Learning Accelerator related IPs design are highly desirable
5.Experience with all phases of frontend architecture, design and validation
6.RTL Coding, design reviews, SYN, CDC, FEV
7.Demonstrated work experience with timing analysis, area and power optimizations, performance analysis, debug ability, ECOs, and post-silicon debug
8.Excellent knowledge of Verilog and popular EDA simulation & implementation tools
9.Good experience in scripting languages like Perl, Unix shell or similar languages
有意者随时联系我，微信 18795875089，或发简历到 [email protected]
欢迎帮忙扩散。
--
--
地点上海北京，薪资 open，欢迎来撩~~
资深 /高级芯片验证工程师
提交简历
工作地点：北京、上海 工作经验：5 或 3 年 教育经历：硕士 工作性质：全职
职位描述
1.Develop test plans, tests and verification infrastructure for complex IP's/sub-system/SOC's
2.Create verification environment for both directed and random verification
3.Create reusable bus functional models, monitors, checkers and scoreboards
4.Drive functional coverage driven verification closure
5.Work with architects, designers and post-silicon teams
职位要求
1.MS with 5+ or 3+ years of experience in design verification
2.Experience with RISC CPU (RISCV/MIPS/ARM) related IPs verification are highly desirable
3.Experience with USB/MIPI_CSI/MIPI_DSI or other high speed interface IPs verification are highly desirable
4.Experience with Deep Learning Accelerator related IPs verification are highly desirable
5.Excellent knowledge of popular EDA simulation tools (VCS or equivalent simulation tools, debug tools like Debussy, Simvision)
6.Experience in System Verilog or similar HVL is highly desirable
7.C++ programming language experience desirable
8.Scripting knowledge (Perl/shell)
9.Excellent communication skills and ability to lead highly competent team.
资深 /高级芯片设计工程师
工作地点：北京、上海 工作经验：5 或 3 年 教育经历：硕士 工作性质：全职
职位描述
1.Participate in RISCV or Deep Learning Accelerator or other SOC IP design for all frontend phase
2.Specification define
3.RTL implementation
4.Analysis and optimization for performance
5.Analysis and optimization for power
6.Analysis and optimization for timing
7.Design flow: lint/synthesis/sta/formal check
8.Silicon debugging
职位要求
1.MS with 5+ or 3+ years of experience in ASIC design
2.Experience with RISC CPU (RISCV/MIPS/ARM) related IPs design are highly desirable
3.Experience with USB/MIPI_CSI/MIPI_DSI or other high speed interface IPs design are highly desirable
4.Experience with Deep Learning Accelerator related IPs design are highly desirable
5.Experience with all phases of frontend architecture, design and validation
6.RTL Coding, design reviews, SYN, CDC, FEV
7.Demonstrated work experience with timing analysis, area and power optimizations, performance analysis, debug ability, ECOs, and post-silicon debug
8.Excellent knowledge of Verilog and popular EDA simulation & implementation tools
9.Good experience in scripting languages like Perl, Unix shell or similar languages
有意者随时联系我，微信 18795875089，或发简历到 [email protected]
欢迎帮忙扩散。
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