@xz410236056 这个除法我记得是用 MicroCode 实现的，而 FMAD 是纯硬件电路。这篇文章里面讨论了这个问题：

https://stackoverflow.com/questions/40354978/why-does-c-code-for-testing-the-collatz-conjecture-run-faster-than-hand-writte/

里面有人给出了数据：
乘法：
Also mul rbx on the OP's Haswell CPU is 2 uops with 3c latency (and 1 per clock throughput). imul rcx, rbx, 3 is only 1 uop, with the same 3c latency. Two ADD instructions would be 2 uops with 2c latency.
除法：
e.g. on the OP's Haswell CPU: DIVSD is 1 uop, 10-20 cycles latency, one per 8-14c throughput. div r64 is 36 uops, 32-96c latency, and one per 21-74c throughput. Skylake has even faster FP division throughput (pipelined at one per 4c with not much better latency), but not much faster integer div.

新的 x86 和 x64 的指令集和架构设计有很多优化和变更，我也没有怎么关注这方面最新的动态，但基本上都默认了除法比乘法慢很多。